Dual bit cells are known in the art although they are not common. Some dual bit cells have multiple threshold levels, where every two threshold levels together store a different bit. Others store one bit on either side of the cell. A dual bit cell of the latter kind, known as nitride read only memory (NROM) cell, is described in Applicant's copending U.S. patent application, Ser. No. 08/905,286, entitled "Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping" which was filed Aug. 1, 1997 and was assigned to the common assignee of the present invention. The disclosure of the above-identified application is incorporated herein by reference.
FIG. 1, to which reference is now made, schematically illustrates the dual bit NROM cell. The cell has a single channel 100 between two bit lines 102 and 104 but two separated and separately chargeable areas 106 and 108. Each area defines one bit. For the dual bit cell of FIG. 1, the separately chargeable areas 106 and 108 are found within a nitride layer 110 formed in an oxide-nitride-oxide sandwich (layers 109, 110 and 111) underneath a polysilicon layer 112.
To read the left bit, stored in area 106, right bit line 104 is the drain and left bit line 102 is the source. This is known as the "read through" direction. The cell is designed to ensure that, in this situation, only the charge in area 106 will affect the current in channel 100. To read the right bit, stored in area 108, the cell is read in the opposite direction. Thus, left bit line 102 is the drain and right bit line 104 is the source.
Like floating gate cells, the cell of FIG. 1 is erasable and programmable. Thus, the charge stored in areas 106 and 108 can change over time in response to a user's request.